Artix-7

The Artix-7 measurement setup is based on the Chipwhisperer CW305 board from NewAE.

The FPGA bitstream used to perform the acquisitions has been generated using the Xilinx Vivado Toolset (v2022.1 64-bit) and the following modifications have been applied compared to the default toolflow parameters:

• HDL annotation:
  • attribute DONT_TOUCH set for every module.
  • attribute KEEP_HIERARCHY set for every module.
• Synthesis parameters:
  • flatten_hierarchy set to none
  • gated_clock_conversion set to off
  • bufg set to 12
  • directive set to Default
  • no_retiming checked
  • fsm_extraction set to auto
  • keep_equivalent_registers checked
  • ressource_sharing set to off
  • no_lc checked
  • no_srlextract checked
• Implementation parameters:
  • opt_design related:
    • is_enabled unchecked
  • phys_opt_design related:
    • is_enabled unchecked

The provided datasets contain power traces that have been acquired by measuring the voltage drop accross the \( 100 m \Omega \) shunt resistor R27. The low noise amplified signal point X4 is measured by a digital oscilloscope through a SMA connector. An external low noise power supply Keysight E36102B is used in order to avoid the noise generated by the onboard (switching) power supply. In particular, a continuous DC voltage of 1V is provided through the dedicated banana jacks on the board (and the switch SW1 is configured accordingly).

The digital oscilloscope used is a PicoScope 6242E. The phase of the clocks used by the target FPGA and the oscilloscope are matched in order to reduce the level of noise induced by clock jitter. In particular, the onboard CDCE906 PLL module is configured to generate two clocks signals based on the 12MHz onboard crystal. The first is the FPGA clock, running at 1.5625MHz that is generated by the PLL1 and fed to the port N13 on the FPGA. The second is a 10MHz clock signal, generated by the PLL0 and fed routed to the X6 SMA connector. The later is then forwarded to the PicoScope 10MHz clock reference input port. A single measurement channel (channel A) is used to perfom the measurement and the trigger signal is fed from the onboard test point TP1 to the oscilloscope AUX trigger port.

The power traces are sampled at 5GHz (resulting in 3200 samples per target clock cycle) using a vertical resolution of 10 bits. Two steps of pre-processing are applied before storing the measurements: first, a re-alignement algorithm based on a maximum correlation is used in order to improve the SNR. In particular, the shift maximising the correlation of each trace with a reference trace is computed and applied for each collected trace. Second, sequential time samples are aggregated (i.e., summed) in order to reduce the dataset storing size. The practical reduction ratio equals 16, resulting in a practical sampling frequency of 312.5MHz with a vertical resolution of 14 bits.

The Vivado project used to generate the bitstream of the target FPGA is available on github. The acquisition setup relies on a tweaked version of the chipwhisperer CW305 firmware. The latter is also available on github. In addition to adding genericity to the acquisition configuration, it has also been modified to be able to acquire multiple datasets while limiting the biases that can occur during long measurement campaigns.